1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a trench isolation structure.
2. Description of the Related Art
A semiconductor integrated circuit uses a trench isolation structure as shown in FIG. 20 for example, for isolating multiple semiconductor elements from each other.
A semiconductor device generally denoted at 2000 includes a p− substrate 1. The p− substrate 1 seats an n− layer 2 in which a trench 3 is formed which reaches the p− substrate 1. A p+ region 5 is formed in wall surfaces of the trench 3, and a buried electrode 31 is disposed in the p+ region 5. Further, there is an n+ buried layer 4 disposed between the p− substrate 1 and the n− layer 2. The back surface of the p− substrate 1 seats a back electrode 15 (JPB 2004-6555).